Chip Services
Products
- Automotive and Industrial control
- Information Security
- Edge Computing& Network Communication
Products
Resources
Language
Chip Services
Products
Resources
Language
| CPU Model | C0 | C2000 | C8000 | C9000 | C9500 | C9800 | CRV4 | CRV4H | CRV7（GHz） | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Manufacturing Process (um) | 0.18 | 0.09GP | 0.04GP | 0.13 | 0.065 | 0.065 | 0.045 | 0.028 | 0.028 | 0.014 | 0.014 | 0.028 | 0.04 | 0.012 |
| Pipeline Stages | 3 | 5 | 7 | 9 | 7 | 7 | 3 | 3 | 8 | |||||
| Instructions Issued Per Cycle | 1 | 2 | 4(3 integer + 1 floating-point units) | 2 | 2 | 1 | 1 | 2 | ||||||
| Number of Parallel Execution Units | 1 | 3 | 7(5 integer + 2 floating-point units) | 6(5 integer + 1 floating-point units) | 6(5 integer + 1 floating-point units) | 1 | 1 | 1 | ||||||
| CACHE(KB) | -- | 0/4/8/16/32 | 16/32 | 32+32 | 32+32 | 32+32 | Configurable | Configurable | 32+32 | |||||
| TLB | -- | 64 | 64 | 1024 | 512 | 512 | -- | -- | 512 | |||||
| General Purpose Registers | 16x32 | 32x32 | 32x32 | 32x32 | 32x32 | 32x64 | 32x32 | 32x32 | 32x64 | |||||
| Bus Protocol | AHB-Lite | PLB4 | PLB4 | PLB6 | CoreNet | CoreNet | AHB | AHB | AXI | |||||
| Other Features | Configurable | L2 Cache: 128K-1M(256K) | L2 Cache: 128KB | L2 Cache: 256KB | TCM/PMP/PMA/BP/FPU | TCM/PMP/PMA/SIMD/DSP/BP/FP | TCM/PMP/SIMD/FPU/BP | |||||||
| Frequency (MHz) | 50 | 300 | 400 | 200 | 400 | 750 | 850 | 1000 | 1200 | 1333 | 1200 | 650 | 250 | 1500 |
| Power Consumption (mW/MHz) | 0.05 | 0.096 | 0.027 | -- | -- | 0.6(actual measurement) | -- | 0.61 | 0.6 | 0.42 | 0.5 | 0.041 | 0.066 | 0.26 |
| Area (mm2) (Including L1 Cache) | 0.25 |
1.2(32KB cache) 0.26(excluding cache) |
0.38(32KB cache) 0.072(excluding cache) |
8.3 | 2.5 | 3.5 | 2.4 |
3(Including) L1+L2) |
5（Including L1+L2） | 1.7（Including L1+L2） | 1.9（Including L1+L2） | 0.24 | 0.28 | 4 |
| Gate Count | 12～20K(+3K for divider, optional) | 430K(32KB cache)90K(excluding cache) | 300K(excluding L1cache) | 800K(excluding L1&L2 cache)V6-760 Logic 50% | 900K(Including L1&L2 cache,no mbff) | 600K(Including L1&L2 cache,with mbff cell) | 700K(Including L1&L2 cache,with mbff cell) | 140K | 160K | 1200K | ||||
| Dhrystone2.1(DMIPS/MHz) | 0.81 | 1.5 | 2 | 2.7 | 2.5 | 3 | 1.7 | 1.7 | 3.2（single core） | |||||
| IP Names | Descriptions |
|---|---|
| Memory Controllers | |
| DDR3MC | DDR3 Controller |
| DDR2MC | DDR2 Controller |
| DDR4 | DDR4 Controller |
| SNFC | Serial NorFlash Access Controller |
| GPIO2AHB | Configurable GPIO Controller |
| EBC | External Bus Controller |
| Bus Controllers | |
| PLB6DMA | DMA PLB6 Bus DMA |
| PLB4DMA | PLB4 Bus/OPB Bus DMA |
| SRAM2PLB4 | On-chip SRAM Access Controller for PLB4 Bus |
| P6BC | PLB6 Bus Controller ( Up to 16 PLB6 Masters) |
| DCRARB4M | DCR Bus Controller (Up to 4 DCR Masters) |
| PLB4ARB8M | PLB4 Bus Controller (Up to 8 PLB4 Masters) |
| OPBARB4M | OPB Bus Controller (Up to 4 OPB Masters) |
| AMBA Bus Matrix | Configurable AMBA Bus Controller |
| AHBXPLB4 Bridge | Bridge Bidirectional AHB/PLB4 Bus Bridge |
| PLB6PLB4 Bridge | Bridge Bidirectional PLB6/PLB4 Bus Bridge |
| PLB42OPB Bridge | Bridge PLB4->OPB Bus Bridge |
| On-chip Functional Modules | |
| MPIC | Multi-Processor Interrupt Controller |
| UIC | Unified Interrupt Controller |
| MCMAL | DMA EMAC Data Transfer DMA |
| RESET | Reset Controller with Multiple Sources |
| INTC | Interrupt Controller with 40 Sources |
| PIT | Periodic Interval Timer |
| WDT | Watchdog Timer |
| EPORT | 8 External Interrupt Sources (Configurable for Edge/Level Trigger) |
| PWM | Pulse Width Modulator |
| Communication Interfaces | |
| EMAC | Ethernet Media Access Controller |
| PCIXS2PLB4 | PCIX Bus/PLB4 Bus Bridge |
| PCIE EP/RC | PCIE RootComplex/EndPoint Controller (PCIE 3.0) |
| AHCI | Serial ATA Advanced Host Controller Interface (SATA 2.0) |
| ISO7816(USI) | Smart Card Control Module, Supports Card and Reader Modes |
| I2C | Control Module, Supports Standard/Fast/High-Speed Modes |
| CAN | CAN Bus Interface Controller (Supporting CAN 2.0B) |
| SPI | Serial Peripheral Interface Controller (Supporting Master/Slave Modes) |
| UART(SCI) | Serial Communication Interface Controller (Supporting Full-Duplex Operation) |
| GPIO | GPIO Interface |
| USB2.0 | Supporting HOST/OTG/DEV |
| SD2.0 | SD Device Controller |
| SWP | Single-Wire Protocol Controller (Supports V9.2.0) |
| RAPID IO 2.2 | RapidIO 2.2 Controller |
| SATA 3.0 HOST | SATA Host Controller |
| SATA 3.0 DEV | SATA Device Controller |
| USB 3.0 | USB 3.0 Controller |
| FlexRay | FlexRay Controller |
| LIN | LIN Bus Interface Controller |
| 1553B | 1553B Controller |
| PCIE 3.0 | PCIE RootComplex/EndPoint Controller (PCIE 3.0) |
| Serdes | Serdes with High-Speed Interface PCS and Ancillary Logic |
| Aurora | Aurora |
| Display Control | |
| DB9000 | LCD Controller |
| Algorithm Modules | |
| BCH Accelerator | BCH Hardware Accelerator |
| CRC Accelerator | CRC Hardware Accelerator |
| DPAA | Network Processing Acceleration Architecture |
| QUICC | Communications Co-Processor Engine |
| RSCP | Reconfigurable Symmetric Cryptographic Processor |
| Public-Key Algorithm Acceleration Engine | Supporting SM2/SM9/ECC/RSA/DH Key Sharing |
| Symmetric Algorithm Acceleration Engine | Supporting SM1/SM4/SM6/SSF33/AES/DES/3DES |
| Hash Algorithm Acceleration Engine | Supporting SM3/MD5/HMAC/SHA0/SHA1/SHA2(224/256/384/512) |
| Analog Modules | |
| PLL | Phase-Locked Loop |
| TRNG | 4Mbps True Random Number Generator |
| IICGF | IIC Clock Glitch Filter |
| POR | Power-On Reset |
| ADC | ADC with 12-bit Precision, 1M Sampling Rate |
| OSC | On-chip Oscillator |
| VR | Voltage Regulator |
| VD | Voltage Detection |
| FD | Frequency Detection |
| TD | Temperature Detection |
| LD | Light Detection |
Search
Contact
